Embodiments of the present invention relate to a method of manufacturing a semiconductor device.
Semiconductor memory devices include a plurality of unit cells that include a capacitor and a transistor. The capacitor is used to store data temporarily, and the transistor is used to transfer data between the capacitor and a bit line in response to a control signal (a word line). The transistor has three parts; a gate, a source, and a drain. Charges move between the source and drain according to a control signal input to the gate. The charges move between the source and drain through a channel region.
When a conventional transistor is fabricated on a semiconductor substrate, the gate is formed on the semiconductor substrate and then the source and drain are formed at both sides of the gate by implanting impurities into the semiconductor substrate. Smaller unit cells are being developed to facilitate the increasing storage capacity and degree of integration of semiconductor memory devices. As a result, the design rule of a capacitor and transistor included in the unit cell is reduced, and thus a channel length of a cell transistor decreases accordingly. When applied to conventional transistors, the reduced channel length may lead to problems such as a short channel effect and drain induced barrier lowering (DIBL) Such phenomena caused due to reduction of the channel length can be overcome when a threshold voltage is maintained. Conventionally, as the channel length is shortened, a doping concentration of an impurity in a region in which the channel region is to be formed is increased.
However, as the design rule is reduced below 100 nm, the increased concentration of doping ions in an active region causes an increase to an electric field in a storage node junction, leading to degradation of a refresh characteristic. A cell transistor having a three dimensional channel structure, in which a channel having a long channel length is established in a vertical direction to maintain a channel length of a cell transistor even when the design rule is reduced, has been developed to help overcome such issues. That is, even when there is limited space for a channel in a horizontal direction, the channel length is established in the vertical direction to reduce a doping concentration, thereby preventing refresh characteristics from being degraded.
In addition, with the increasing degree of integration of semiconductor devices, a distance between a word line and a bit line connected to the cell transistor is reduced. Thus, parasitic capacitance is increased, and a sensing margin of a sense amplifier configured to amplify data transferred through the bit line is deteriorated, which has a negative effect on the operational reliability of the semiconductor device. To reduce the parasitic capacitance between the bit line and the word line, a buried word line structure, in which a word line is formed only in a recess and not on a semiconductor substrate, has been suggested. The buried word line structure, in which a word line including a conductive material formed within the recess and an insulating layer covering the conductive material is formed within a semiconductor substrate, allows the word line to make an accurate electrical separation from a bit line formed on the semiconductor substrate in which a source and drain are formed.
As described above, the buried word line structure has an overlapping region between the source and drain junctions and the word line, so gate induced drain leakage (GIDL) occurs in the is overlapping region. When GIDL is increased, accumulated charges are discharged and a memory retention characteristic is degraded.